1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to read-only memories (hereinafter referred to as "ROMs").
2. Description of the Related Art
ROMs for use in storing various items of program data generally include a plurality of MIS transistors in the form of a matrix of gate wiring source regions and drain regions.
Such ROMs are in predetermined to be broken in the source-drain circuit of the transistors, or short-circuited between the source and drain regions, or inactivated between the source and drain regions with an increased thickness of the insulating film under the gate wiring (i.e., gate insulating film). Whereby currents between the drain and the source are detected or non-detected and hence the memory data unit is stored as a "1" or a "0".
The so-called LOCOS (Local Oxidation Silicon) process (Electronics, Dec. 20, p. 45, (1971)); "MOS Device," Complete Book of Electronics Techniques, pp. 290-291, Kogyo Chosakai (Industrial Research Association, (1976)) is used for forming thick insulating films for use in ROMs.
FIG. 2 (a) is a plan view of a conventional silicon-gate ROM, FIG. 2 (b) is a view for the section taken along the line A-A' in FIG. 2 (a), and FIG. 2 (c) is a view for the section taken along the line B-B' in FIG. 2 (a). Oxide films 2a and 2b are formed by the LOCOS process on the cell separating regions and inactive transistor gate regions of a semiconductor substrate 1, and a gate oxide film 3 is formed on the gate regions thereof to provide active transistors. Polysilicon gate wiring 4 is then formed on the substrate 1, and semiconductor regions, which provide source regions 5a and drain regions 5b, are thereafter formed on the substrate 1 by using the oxide films 2a and 2b and the gate wiring 4 for masking. Subsequently, an interlayer insulating film 6 of NSG, BPSG or the like is formed on the substrate 1, contact holes 7 are formed in the interlayer insulating film 6 on the drain regions 5b, and metal wiring 8 is thereafter provided in contact with the drain regions 5b.
Thus, the oxide film 2b having a larger thickness than the gate film 3 is formed in the gate regions (.beta.) of the inactive transistors by the LOCOS process, so that when such a transistor is selected for reading out data, no current flows between the source region 5a and the drain region 5b. This corresponds, for example, to the memory data unit "0". Accordingly various items of data can be stored using the combination of this unit with the memory data unit. For example, a "1" may be stored at the gate region (.alpha.) of the active transistor.
However, when thick insulating films are formed by the LOCOS process, the film formed invariably has a larger width than is intended because of the influence from the internal diffusion of oxygen during thermal oxidation. An increase in the ratio of the width is greater when the specified width is smaller.
Because the ROM cells have such a thick insulating film in the cell separating region and the gate inactivating film are limited in design by the increase in the film width, limitations are imposed on the provision of ROMs having a greater complexity.
This will be described more specifically with reference to the conventional ROM described which must have pitches, according to the 1.0-.mu.m rule, for example as illustrated in FIG. 2 (b), the horizontal pitch required is 3.6 .mu.m, which is a total of 1 .mu.m for a space a of the contact hole 7, 0.4 .mu.m for each of two portions of allowance b for the alignment of the contact hole 7 with the drain region 5b, 0.4 .mu.m for each of two edge portions c of the oxide film 2a formed by the LOCOS process and provide a cell separating region, and 1 .mu.m for a space d of the oxide film 2a formed by the LOCOS process to provide a cell separating region.
With reference to FIG. 2 (c), the vertical pitch for the active transistor is 3.2 .mu.m, which is a total of 0.5 .mu.m for a half portion A of the source region 5a, 0.8 .mu.m for an allowance B for the aligment of the gate 4 with the source area 5a, 1 .mu.m for the width C of the gate 4, 0.4 .mu.m for an allowance D for aligning the gate 4 with the contact hole 7, and 0.5 .mu.m for one half portion E of the contact hole 7. With the inactive transistor, the vertical pitch is 3.2 .mu.m, which is a total of 0.5 .mu.m for the other half portion E of the contact hole 7, 0.4 .mu.m for an allowance D for aligning the gate wiring 4 with the contact hole 7, 0.4 .mu.m for each of two edge portions F of the oxide film 2b formed by the LOCOS process in the gate region of the inactive transistor, 1 .mu.m for a space G of the oxide film 2b, and 0.5 .mu.m for a half portion A of the source region 5a. The pitch required is 3.2 .mu.m regardless of whether the transistor is active or inactive.
There is a need to provide spaces which are not directly relevant to the separation of cells or to the inactivation of transistors, i.e. the edge portions c of the oxide film 2a and the edge portions F of the oxide film 2b. Consequently, each cell requires a large space (in the above case, 3.6 .mu.m .times.3.2 .mu.m=11.52 .mu.m.sup.2) which is objectionable in providing compact ROMs of higher complexity.